6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pcix.h>
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static void pcix_tune_dev(struct device *dev)
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{
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u32 status;
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u16 orig_cmd, cmd;
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unsigned int cap, max_read, max_tran;
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if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
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return;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!cap)
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return;
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printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev));
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status = pci_read_config32(dev, cap + PCI_X_STATUS);
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orig_cmd = cmd = pci_read_config16(dev, cap + PCI_X_CMD);
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max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
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max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
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if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
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cmd &= ~PCI_X_CMD_MAX_READ;
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cmd |= max_read << 2;
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}
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if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
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cmd &= ~PCI_X_CMD_MAX_SPLIT;
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cmd |= max_tran << 4;
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}
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/* Don't attempt to handle PCI-X errors. */
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cmd &= ~PCI_X_CMD_DPERR_E;
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/* Enable relaxed ordering. */
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cmd |= PCI_X_CMD_ERO;
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if (orig_cmd != cmd)
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pci_write_config16(dev, cap + PCI_X_CMD, cmd);
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}
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static void pcix_tune_bus(struct bus *bus)
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{
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struct device *child;
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for (child = bus->children; child; child = child->sibling)
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pcix_tune_dev(child);
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}
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const char *pcix_speed(u16 sstatus)
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{
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static const char conventional[] = "Conventional PCI";
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static const char pcix_66mhz[] = "66MHz PCI-X";
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static const char pcix_100mhz[] = "100MHz PCI-X";
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static const char pcix_133mhz[] = "133MHz PCI-X";
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static const char pcix_266mhz[] = "266MHz PCI-X";
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static const char pcix_533mhz[] = "533MHZ PCI-X";
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static const char unknown[] = "Unknown";
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const char *result;
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result = unknown;
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switch (PCI_X_SSTATUS_MFREQ(sstatus)) {
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case PCI_X_SSTATUS_CONVENTIONAL_PCI:
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result = conventional;
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break;
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case PCI_X_SSTATUS_MODE1_66MHZ:
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result = pcix_66mhz;
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break;
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case PCI_X_SSTATUS_MODE1_100MHZ:
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result = pcix_100mhz;
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break;
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case PCI_X_SSTATUS_MODE1_133MHZ:
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result = pcix_133mhz;
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break;
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case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
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case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
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case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
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result = pcix_266mhz;
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break;
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case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
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case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
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case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
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result = pcix_533mhz;
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break;
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}
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return result;
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}
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void pcix_scan_bridge(struct device *dev)
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{
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unsigned int pos;
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u16 sstatus;
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do_pci_scan_bridge(dev, pci_scan_bus);
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/* Find the PCI-X capability. */
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pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
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if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
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pcix_tune_bus(dev->link_list);
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/* Print the PCI-X bus speed. */
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printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary,
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pcix_speed(sstatus));
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}
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/** Default device operations for PCI-X bridges */
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static struct pci_operations pcix_bus_ops_pci = {
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.set_subsystem = 0,
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};
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struct device_operations default_pcix_ops_bus = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.scan_bus = pcix_scan_bridge,
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.reset_bus = pci_bus_reset,
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.ops_pci = &pcix_bus_ops_pci,
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};
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