0a5971c91b
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
40 lines
1 KiB
C
40 lines
1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <main_decl.h>
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#include <program_loading.h>
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#include <soc/intel/common/util.h>
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#include <fsp/util.h>
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void main(void)
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{
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/* Call TempRamExit FSP API if enabled. */
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if (IS_ENABLED(CONFIG_FSP_CAR))
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fsp_temp_ram_exit();
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console_init();
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/* Recover cbmem so infrastruture using it is functional. */
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cbmem_initialize();
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/* Display the MTRRs */
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
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soc_display_mtrrs();
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/* Load and run ramstage. */
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run_ramstage();
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}
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