d2cdfff63b
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _PCI_MMIO_CFG_H
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#define _PCI_MMIO_CFG_H
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#include <stdint.h>
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#include <device/mmio.h>
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#include <device/pci_type.h>
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#if !defined(__ROMCC__)
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/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
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* prevent some sub-optimal constant folding. */
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extern u8 *const pci_mmconf;
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/* Using a unique datatype for MMIO writes makes the pointers to _not_
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* qualify for pointer aliasing with any other objects in memory.
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*
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* MMIO offset is a value originally derived from 'struct device *'
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* in ramstage. For the compiler to not discard this MMIO offset value
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* from CPU registers after any MMIO writes, -fstrict-aliasing has to
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* be also set for the build.
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*
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* Bottom 12 bits (4 KiB) are reserved to address the registers of a
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* single PCI function. Declare the bank as a union to avoid some casting
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* in the functions below.
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*/
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union pci_bank {
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uint8_t reg8[4096];
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uint16_t reg16[4096 / sizeof(uint16_t)];
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uint32_t reg32[4096 / sizeof(uint32_t)];
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};
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static __always_inline
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volatile union pci_bank *pcicfg(pci_devfn_t dev)
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{
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return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)];
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}
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static __always_inline
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uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg8[reg];
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}
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static __always_inline
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uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
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}
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static __always_inline
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uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
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}
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static __always_inline
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void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
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{
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pcicfg(dev)->reg8[reg] = value;
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}
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static __always_inline
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void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
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{
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pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value;
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}
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static __always_inline
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void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
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{
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pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value;
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}
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#endif /* !defined(__ROMCC__) */
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#if CONFIG(MMCONF_SUPPORT)
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/* Avoid name collisions as different stages have different signature
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* for these functions. The _s_ stands for simple, fundamental IO or
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* MMIO variant.
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*/
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static __always_inline
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uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config8(dev, reg);
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}
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static __always_inline
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uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config16(dev, reg);
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}
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static __always_inline
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uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config32(dev, reg);
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}
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static __always_inline
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void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
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{
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pci_mmio_write_config8(dev, reg, value);
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}
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static __always_inline
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void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
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{
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pci_mmio_write_config16(dev, reg, value);
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}
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static __always_inline
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void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
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{
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pci_mmio_write_config32(dev, reg, value);
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}
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#endif
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#endif /* _PCI_MMIO_CFG_H */
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