Felix Held 82a0a63f99 soc/amd/picasso/southbridge: make GPP clock outputs configurable ... Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2020-08-31 06:42:39 +00:00
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amd	soc/amd/picasso/southbridge: make GPP clock outputs configurable	2020-08-31 06:42:39 +00:00
cavium	symbols: Change implementation details of DECLARE_OPTIONAL_REGION()	2020-08-27 22:11:17 +00:00
intel	PCI IDs: Add PCI ID for CML DPTF/DTT PCI device	2020-08-29 01:59:02 +00:00
mediatek	soc/mediatek/mt8192: Use SPI-NOR as flash controller	2020-08-28 04:44:56 +00:00
nvidia	{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file	2020-08-31 06:36:18 +00:00
qualcomm	src: Remove unused 'include <delay.h>'	2020-08-18 12:19:18 +00:00
rockchip	src/soc/rockchip: Add missing <{stddef,stdint}.h>	2020-07-29 09:37:22 +00:00
samsung	src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>	2020-07-29 09:34:55 +00:00
sifive	soc/sifive: Drop unneeded empty lines	2020-08-24 09:16:48 +00:00
ti	cpu/ti/am335x: Move from cpu to soc in tree	2020-08-19 07:17:37 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00