Arthur Heymans 15e1b39e6e nb/intel/pineview: Don't use PCI operations on the pci_domain device ... pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27243 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-08-01 12:12:50 +00:00
..
acpi	sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables	2018-06-29 07:45:30 +00:00
acpi.c
bootblock.c	src/northbridge: Add and update license headers	2018-05-29 22:36:37 +00:00
chip.h	src/northbridge: Add and update license headers	2018-05-29 22:36:37 +00:00
early_init.c	nb/intel/pineview: Move to early cbmem	2017-04-24 19:46:43 +02:00
gma.c	northbridge/intel: Remove unneeded includes	2018-06-04 02:38:01 +00:00
iomap.h
Kconfig	arch/x86: Make RELOCATABLE_RAMSTAGE the default	2018-06-06 12:29:19 +00:00
Makefile.inc	nb/intel/pineview: Switch to POSTCAR_STAGE	2018-06-05 07:49:09 +00:00
northbridge.c	nb/intel/pineview: Don't use PCI operations on the pci_domain device	2018-08-01 12:12:50 +00:00
pineview.h	nb/intel/pineview: Enable and allocate 8M for TSEG	2018-06-07 06:42:14 +00:00
ram_calc.c	nb/intel/pineview: Switch to POSTCAR_STAGE	2018-06-05 07:49:09 +00:00
raminit.c	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
raminit.h