coreboot-kgpe-d16/src
Caveh Jalali 173493784d mb/google/volteer: Pull up GPP_D16 instead of driving it
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.

BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
	can read SD cards.

Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-10 21:49:44 +00:00
..
acpi src/acpi: Add missing <{stdbool,stdint}.h> 2020-07-29 09:37:10 +00:00
arch arch/x86/pirq_routing.c: Drop unneeded `continue` 2020-08-06 11:22:11 +00:00
commonlib src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
console console: Update for vboot before bootblock 2020-06-15 22:07:12 +00:00
cpu cpu/intel/common: Add `intel_ht_supported` function 2020-08-06 22:33:02 +00:00
device src: Use space after 'if', 'for' 2020-08-05 11:37:00 +00:00
drivers drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable 2020-08-06 04:24:24 +00:00
ec ec/lenovo/h8: Align macro values in one column 2020-07-26 21:40:00 +00:00
include soc/intel/common: Include Alder Lake SATA controller device IDs 2020-08-10 06:30:39 +00:00
lib gpio: Pull down HiZ pins after reading tristate GPIO strapping 2020-08-06 23:54:41 +00:00
mainboard mb/google/volteer: Pull up GPP_D16 instead of driving it 2020-08-10 21:49:44 +00:00
northbridge nb/intel/sandybridge: Drop inexistent device from DMAR 2020-08-06 11:16:46 +00:00
security security/intel/txt: Fix variable MTRR handling 2020-08-07 11:56:29 +00:00
soc soc/intel/apollolake: Rename UART irqs 2020-08-10 10:45:46 +00:00
southbridge sb/intel/lynxpoint: Use PCI bitwise ops 2020-08-07 11:02:43 +00:00
superio superio/ite: allow 24 MHz clock for external sensor interface 2020-08-10 12:44:17 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc 2020-08-08 20:13:37 +00:00
Kconfig arch/x86: Remove RELOCATABLE_RAMSTAGE 2020-07-06 06:17:47 +00:00