coreboot-kgpe-d16/src/mainboard/siemens
Mario Scheithauer 17641208f5 mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-04 10:22:07 +00:00
..
chili mb/siemens/chili: Drop redundant Kconfig select 2021-10-27 15:04:26 +00:00
mc_apl1 mb/*: Specify type of VARIANT_DIR once 2021-07-26 14:07:38 +00:00
mc_ehl mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree 2021-11-04 10:22:07 +00:00
Kconfig mb/*/Kconfig: Factor out MAINBOARD_VENDOR 2020-03-03 10:15:22 +00:00
Kconfig.name