188e3c2ff0
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/sb800/sb800.h>
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u8 is_dev3_present(void);
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void set_pcie_dereset(void);
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void set_pcie_reset(void);
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void enable_int_gfx(void);
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/* GPIO6. */
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void enable_int_gfx(void)
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{
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u8 byte;
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volatile u8 *gpio_reg;
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pm_iowrite(0xEA, 0x01); /* diable the PCIB */
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/* Disable Gec */
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byte = pm_ioread(0xF6);
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byte |= 1;
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pm_iowrite(0xF6, byte);
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/* make sure the fed80000 is accessible */
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byte = pm_ioread(0x24);
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byte |= 1;
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pm_iowrite(0x24, byte);
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gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
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*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
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*(gpio_reg + 170) = 0x1; /* gpio_gate */
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gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
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*(gpio_reg + 0x6) = 0x8;
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*(gpio_reg + 170) = 0x0;
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}
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/*
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* Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
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* pull it up before training the slot.
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***/
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void set_pcie_dereset(void)
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{
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/* GPIO 50h reset PCIe slot */
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/*
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u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
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u8 byte = ~(1 << 5);
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byte |= ~(1 << 6);
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*addr = byte;
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*/
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}
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void set_pcie_reset(void)
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{
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/* GPIO 50h reset PCIe slot */
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/*
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u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
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u8 byte = ~((1 << 5) | (1 << 6));
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*addr = byte;
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*/
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}
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u8 is_dev3_present(void)
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{
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return 0;
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}
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#if 0 /* not tested yet. */
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/********************************************************
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* bimini uses SB800 GPIO9 to detect IDE_DMA66.
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* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
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* get the cable type, 40 pin or 80 pin?
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********************************************************/
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static void get_ide_dma66(void)
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{
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u8 byte;
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/*u32 sm_dev, ide_dev; */
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device_t sm_dev, ide_dev;
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0xA9);
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byte |= (1 << 5); /* Set Gpio9 as input */
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pci_write_config8(sm_dev, 0xA9, byte);
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ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
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byte = pci_read_config8(ide_dev, 0x56);
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byte &= ~(7 << 0);
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if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
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byte |= 2 << 0; /* mode 2 */
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else
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byte |= 5 << 0; /* mode 5 */
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pci_write_config8(ide_dev, 0x56, byte);
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}
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#endif /* get_ide_dma66() */
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/*************************************************
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* enable the dedicated function in bimini board.
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* This function called early than rs780_enable.
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*************************************************/
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static void bimini_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
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setup_uma_memory();
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set_pcie_dereset();
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enable_int_gfx();
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/* get_ide_dma66(); */
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}
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int add_mainboard_resources(struct lb_memory *mem)
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{
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("AMD Bimini Mainboard")
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.enable_dev = bimini_enable,
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};
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