8a017aa394
Run the command below to fix all occurrences.
git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g'
Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <AGESA.h>
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#include <PlatformMemoryConfiguration.h>
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#include <northbridge/amd/agesa/state_machine.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x01, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x02, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x03, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x05, 0)
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}
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DP0 to HDMI0/DP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
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},
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/* DP1 to high-speed edge connector */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = FALSE;
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}
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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}
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERRIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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#define SEED_WL 0x0E
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WRITE_LEVELING_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
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SEED_WL),
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#define SEED_A 0x12
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
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SEED_A),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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