1943d501b4
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
42 lines
1 KiB
C
42 lines
1 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "arch/romcc_io.h"
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#include "pc80/mc146818rtc_early.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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static void main(void)
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{
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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/* Setup the 8111 */
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amd8111_enable_rom();
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/* Is this a cpu reset? */
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if (cpu_init_detected()) {
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if (last_boot_normal()) {
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asm("jmp __normal_image");
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} else {
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asm("jmp __cpu_reset");
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}
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}
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/* Is this a deliberate reset by the bios */
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else if (bios_reset_detected() && last_boot_normal()) {
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asm("jmp __normal_image");
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}
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/* Is this a secondary cpu? */
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else if (!boot_cpu() && last_boot_normal()) {
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asm("jmp __normal_image");
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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asm("jmp __normal_image");
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}
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}
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