Philipp Hug 199b75f58a arch/riscv: provide a monotonic timer ... The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-09-14 09:28:06 +00:00
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arm	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00
arm64	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00
mips	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00
power8	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00
riscv	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
x86	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00