6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootblock_common.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8786e/it8786e.h>
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#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO)
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#define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1)
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#define SERIAL3_DEV PNP_DEV(0x2e, IT8786E_SP3)
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#define SERIAL4_DEV PNP_DEV(0x2e, IT8786E_SP4)
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#define SERIAL5_DEV PNP_DEV(0x2e, IT8786E_SP5)
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#define SERIAL6_DEV PNP_DEV(0x2e, IT8786E_SP6)
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void bootblock_mainboard_early_init(void)
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{
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ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
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ite_enable_3vsbsw(GPIO_DEV);
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ite_kill_watchdog(GPIO_DEV);
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ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
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/*
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* FIXME:
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* IT8786E has 6 COM ports, COM1/3/5 have default IO base 0x3f8 and
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* COM2/4/6 have 0x2f8. When enabling devices before setting resources
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* from devicetree, the output on debugging COM1 becomes very slow due
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* to the same IO bases for multiple COM ports. For now set different
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* hardcoded IO bases for COM3/4/5/6 ports, they will be set later to
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* desired values from devicetree. They can be also turned off.
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*/
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ite_enable_serial(SERIAL3_DEV, 0x3e8);
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ite_enable_serial(SERIAL4_DEV, 0x2e8);
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ite_enable_serial(SERIAL5_DEV, 0x2f0);
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ite_enable_serial(SERIAL6_DEV, 0x2e0);
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}
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