f2a0be235c
It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.
TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
intel_backlight + acpi_video synchronize, both before and
after suspend.
Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
213 lines
5.2 KiB
Text
213 lines
5.2 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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/* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External(NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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F0ON, 8, // 0x17 - FAN 0 ON Threshold
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F0PW, 8, // 0x18 - FAN 0 PWM value
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F1OF, 8, // 0x19 - FAN 1 OFF Threshold
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F1ON, 8, // 0x1a - FAN 1 ON Threshold
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F1PW, 8, // 0x1b - FAN 1 PWM value
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F2OF, 8, // 0x1c - FAN 2 OFF Threshold
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F2ON, 8, // 0x1d - FAN 2 ON Threshold
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F2PW, 8, // 0x1e - FAN 2 PWM value
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F3OF, 8, // 0x1f - FAN 3 OFF Threshold
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F3ON, 8, // 0x20 - FAN 3 ON Threshold
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F3PW, 8, // 0x21 - FAN 3 PWM value
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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APIC, 8, // 0x28 - APIC Enabled by coreboot
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MPEN, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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PCNT, 8, // 0x2d - Processor count
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 -
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S5U0, 8, // 0x33 - Enable USB0 in S5
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S5U1, 8, // 0x34 - Enable USB1 in S5
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S3U0, 8, // 0x35 - Enable USB0 in S3
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S3U1, 8, // 0x36 - Enable USB1 in S3
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S33G, 8, // 0x37 - Enable 3G in S3
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CMEM, 32, // 0x38 - CBMEM TOC
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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/* TPM support */
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Offset (0x5b),
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TPMP, 8, // 0x5b - TPM Present
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TPME, 8, // 0x5c - TPM Enable
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/* LynxPoint Serial IO device BARs */
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Offset (0x60),
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S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0
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S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0
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S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0
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S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0
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S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0
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S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0
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S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0
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S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0
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S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1
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S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1
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S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1
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S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1
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S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1
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S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1
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S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1
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S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1
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Offset (0xa0),
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CBMC, 32, // 0xa0 - coreboot mem console pointer
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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/* Set flag to enable 3G module in S3 */
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Method (S3GE)
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{
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Store (One, \S33G)
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}
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/* Set flag to disable 3G module in S3 */
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Method (S3GD)
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{
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Store (Zero, \S33G)
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}
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External (\_TZ.SKIN)
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Method (TZUP)
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{
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#ifdef HAVE_THERMALZONE
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/* Update Primary Thermal Zone */
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If (CondRefOf (\_TZ.THRM)) {
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Notify (\_TZ.THRM, 0x81)
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}
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#endif
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/* Update Secondary Thermal Zone */
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If (CondRefOf (\_TZ.SKIN)) {
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Notify (\_TZ.SKIN, 0x81)
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}
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}
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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TZUP ()
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}
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