a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
201 lines
6.5 KiB
C
201 lines
6.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* TODO: Check if this really works for all of the southbridges. */
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#include <stdint.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82371eb.h"
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/**
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* Initialize the IDE controller.
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*
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* Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
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* enable or disable the primary and secondary IDE interface, respectively.
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*
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* Depending on the configuration variable 'ide_legacy_enable' enable or
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* disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
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* registers (this is required for e.g. FILO).
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*
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* @param dev The device to use.
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*/
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static void ide_init_enable(struct device *dev)
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{
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u16 reg16;
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struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
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/* Enable/disable the primary IDE interface. */
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reg16 = pci_read_config16(dev, IDETIM_PRI);
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reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
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pci_write_config16(dev, IDETIM_PRI, reg16);
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printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
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conf->ide0_enable ? "on" : "off");
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/* Enable/disable the secondary IDE interface. */
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reg16 = pci_read_config16(dev, IDETIM_SEC);
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reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
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pci_write_config16(dev, IDETIM_SEC, reg16);
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printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
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conf->ide1_enable ? "on" : "off");
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/* Enable access to the legacy IDE ports (both primary and secondary),
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* and the PCI Bus Master IDE I/O registers.
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* Only do this if at least one IDE interface is enabled.
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*/
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if (conf->ide0_enable || conf->ide1_enable) {
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 = ONOFF(conf->ide_legacy_enable, reg16,
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(PCI_COMMAND_IO | PCI_COMMAND_MASTER));
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pci_write_config16(dev, PCI_COMMAND, reg16);
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printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n",
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conf->ide_legacy_enable ? "on" : "off");
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}
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}
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/**
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* Initialize the Ultra DMA/33 support of the IDE controller.
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*
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* Depending on the configuration variables 'ide0_drive0_udma33_enable',
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* 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
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* 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
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* the respective IDE controller and drive.
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*
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* Only do that if the respective controller is actually enabled, of course.
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*
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* @param dev The device to use.
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*/
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static void ide_init_udma33(struct device *dev)
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{
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u8 reg8;
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struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
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/* Enable/disable UDMA/33 operation (primary IDE interface). */
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if (conf->ide0_enable) {
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reg8 = pci_read_config8(dev, UDMACTL);
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reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0);
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reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
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pci_write_config8(dev, UDMACTL, reg8);
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printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
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"Primary IDE interface", 0,
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conf->ide0_drive0_udma33_enable ? "on" : "off");
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printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
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"Primary IDE interface", 1,
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conf->ide0_drive1_udma33_enable ? "on" : "off");
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}
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/* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
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if (conf->ide1_enable) {
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reg8 = pci_read_config8(dev, UDMACTL);
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reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0);
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reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
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pci_write_config8(dev, UDMACTL, reg8);
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printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
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"Secondary IDE interface", 0,
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conf->ide1_drive0_udma33_enable ? "on" : "off");
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printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
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"Secondary IDE interface", 1,
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conf->ide1_drive1_udma33_enable ? "on" : "off");
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}
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}
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/**
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* IDE init for the Intel 82371FB/SB IDE controller.
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*
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* These devices do not support UDMA/33, so don't attempt to enable it.
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*
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* @param dev The device to use.
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*/
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static void ide_init_i82371fb_sb(struct device *dev)
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{
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ide_init_enable(dev);
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}
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/**
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* IDE init for the Intel 82371AB/EB/MB IDE controller.
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*
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* @param dev The device to use.
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*/
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static void ide_init_i82371ab_eb_mb(struct device *dev)
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{
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ide_init_enable(dev);
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ide_init_udma33(dev);
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}
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/* Intel 82371FB/SB */
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static const struct device_operations ide_ops_fb_sb = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init_i82371fb_sb,
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.scan_bus = 0,
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.enable = 0,
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.ops_pci = 0, /* No subsystem IDs on 82371XX! */
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};
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/* Intel 82371AB/EB/MB */
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static const struct device_operations ide_ops_ab_eb_mb = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init_i82371ab_eb_mb,
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.scan_bus = 0,
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.enable = 0,
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.ops_pci = 0, /* No subsystem IDs on 82371XX! */
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};
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/* Intel 82371FB (PIIX) */
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static const struct pci_driver ide_driver_fb __pci_driver = {
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.ops = &ide_ops_fb_sb,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371FB_IDE,
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};
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/* Intel 82371SB (PIIX3) */
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static const struct pci_driver ide_driver_sb __pci_driver = {
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.ops = &ide_ops_fb_sb,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371SB_IDE,
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};
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/* Intel 82371MX (MPIIX) */
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static const struct pci_driver ide_driver_mx __pci_driver = {
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.ops = &ide_ops_fb_sb,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE,
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};
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/* Intel 82437MX (part of the 430MX chipset) */
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static const struct pci_driver ide_driver_82437mx __pci_driver = {
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.ops = &ide_ops_fb_sb,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE,
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};
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/* Intel 82371AB/EB/MB */
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static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = {
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.ops = &ide_ops_ab_eb_mb,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371AB_IDE,
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};
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