d27c08c289
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
108 lines
3.9 KiB
Text
108 lines
3.9 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip northbridge/intel/i945
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device apic_cluster 0 on
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chip cpu/intel/socket_441
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 00.0 on end # host bridge
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device pci 01.0 off end # i945 PCIe root port
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device pci 02.0 on end # vga controller
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device pci 02.1 on end # display controller
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x05"
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register "pirqb_routing" = "0x07"
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register "pirqc_routing" = "0x05"
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register "pirqd_routing" = "0x07"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x06"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "1"
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register "gpe0_en" = "0x20000601"
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe
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device pci 1c.1 on end # PCIe
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device pci 1c.2 on end # PCIe
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#device pci 1c.3 off end # PCIe port 4
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#device pci 1c.4 off end # PCIe port 5
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#device pci 1c.5 off end # PCIe port 6
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device pci 1d.0 on end # USB UHCI
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device pci 1d.1 on end # USB UHCI
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device pci 1d.2 on end # USB UHCI
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device pci 1d.3 on end # USB UHCI
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device pci 1d.7 on end # USB2 EHCI
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device pci 1e.0 on end # PCI bridge
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#device pci 1e.2 off end # AC'97 Audio
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#device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/lpc47m15x
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device pnp 2e.0 off # Floppy
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end
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device pnp 2e.3 off # Parport
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end
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device pnp 2e.4 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 on
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
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end
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device pnp 2e.7 on # Keyboard+Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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irq 0xf0 = 0x82 # HW accel A20.
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end
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device pnp 2e.8 on # GAME
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# all default
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end
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device pnp 2e.a on # PME
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end
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device pnp 2e.b on # MPU
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end
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end
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end
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#device pci 1f.1 off end # IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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#device pci 1f.4 off end # Realtek ID Codec
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end
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end
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end
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