Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. ... Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2011-08-04 08:10:12 +02:00
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amd	Update AMD SR5650 and SB700	2011-07-22 00:20:59 +02:00
intel	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	2011-08-04 08:10:12 +02:00
via	more ifdef -> if fixes	2011-04-21 20:45:45 +00:00
x86	Add SSE3 dependent code	2011-07-22 08:22:59 +02:00
Kconfig	- Fix shortcoming in Kconfig when handling multiple "choice"s	2010-12-16 23:37:17 +00:00
Makefile.inc	qemu: drop "northbridge.c" from src/cpu/...	2010-03-29 21:17:25 +00:00