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Srinidhi N Kaushik 083379d0f8 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 
Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:

FSPM:
 - PchTraceHubMode
 - CpuTraceHubMode
 - CpuPcieRpEnableMask
FSPS:
 - D3HotEnable
 - D3ColdEnable
 - RtcMemoryLock
 - PchLockDownGlobalSmi
 - PchLockDownBiosInterface
 - PchUnlockGpioPads
 - CpuMpPpi
 - ThcPort0Assignment
 - ThcPort1Assignment

BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 20:28:26 +00:00
..
amd src/vendorcode: Use SPDX for GPL-2.0-only files 2020-04-04 14:58:21 +00:00
cavium src/vendorcode: Use SPDX for GPL-2.0-only files 2020-04-04 14:58:21 +00:00
eltan src/vendorcode: Use SPDX for GPL-2.0-only files 2020-04-04 14:58:21 +00:00
google Drop unnecessary DEVICE_NOOP entries 2020-04-10 11:25:04 +00:00
intel vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 2020-04-11 20:28:26 +00:00
siemens src/vendorcode: Use SPDX for GPL-2.0-only files 2020-04-04 14:58:21 +00:00
Makefile.inc vendorcode/eltan: Add vendor code for measured and verified boot 2019-06-04 10:41:53 +00:00