coreboot-kgpe-d16/src
Rudolf Marek 1b22827cf0 Asus F2A85-M: Fix the _CRS PCI0 bus info
On Asus F2A85-M, the Linux kernel complains that the _CRS method does
not specify the number of PCI busses.

    [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS

Just put there 256. This should be part of re-factoring of the whole
ACPI stuff.

The same change was already done for the AMD Brazos (SB800) boards,
based on commit »Persimmon DSDT: Add secondary bus range to PCI0«
(4733c647) [1].

[1] http://review.coreboot.org/2592

Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3320
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-03 17:50:24 +02:00
..
arch Provide sane Kconfig default for cmos.default. 2013-06-02 23:07:22 +02:00
console console: add support for QEMU's debugcon 2013-06-03 17:32:31 +02:00
cpu haswell: allow for disabled hyperthreading 2013-06-03 17:30:48 +02:00
device Get rid of a number of __GNUC__ checks 2013-05-10 17:31:31 +02:00
drivers pc80/tpm: allow for cache-as-ram migration 2013-05-16 01:29:59 +02:00
ec ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT 2013-04-18 02:47:23 +02:00
include Intel GM45, 945, SNB: Move multiply_to_tsc() to tsc.h 2013-05-25 14:22:06 +02:00
lib cbmem console: use cache-as-ram API and cleanup 2013-05-16 01:30:17 +02:00
mainboard Asus F2A85-M: Fix the _CRS PCI0 bus info 2013-06-03 17:50:24 +02:00
northbridge haswell: fix overflow handling TOUUD 2013-06-03 17:30:09 +02:00
southbridge AMD Geode CS5536: downgrade BIOS_ERR 2013-06-03 17:47:06 +02:00
superio Drop prototype guarding for romcc 2013-05-10 00:06:46 +02:00
vendorcode chromeos: use cache-as-ram migration API for vbnv 2013-05-16 01:30:09 +02:00
Kconfig Kconfig: Remove duplicate entry for USE_OPTION_TABLE 2013-05-23 10:42:41 +02:00