a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
123 lines
2.5 KiB
ArmAsm
123 lines
2.5 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define WAKEUP_BASE 0x600
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#define RELOCATED(x) (x - __wakeup + WAKEUP_BASE)
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/* CR0 bits */
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#define PE (1 << 0)
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#ifdef __x86_64__
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.code64
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#else
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.code32
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#endif
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.globl __wakeup
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__wakeup:
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#ifdef __x86_64__
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.intel_syntax noprefix
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xor rax,rax
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mov ax, ss
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push rax
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mov rax, rsp
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add rax, 8
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push rax
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pushfq
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push 0x10
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lea rax,[rip+3]
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push rax
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iretq
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.code32
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/* disable paging */
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mov eax, cr0
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btc eax, 31
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mov cr0, eax
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/* disable long mode */
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mov ecx, 0xC0000080
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rdmsr
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btc eax, 8
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wrmsr
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.att_syntax prefix
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#endif
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/* First prepare the jmp to the resume vector */
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mov 0x4(%esp), %eax /* vector */
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/* last 4 bits of linear addr are taken as offset */
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andw $0x0f, %ax
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movw %ax, (__wakeup_offset)
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mov 0x4(%esp), %eax
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/* the rest is taken as segment */
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shr $4, %eax
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movw %ax, (__wakeup_segment)
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/* Then overwrite coreboot with our backed up memory */
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cld
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movl 8(%esp), %esi
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movl 12(%esp), %edi
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movl 16(%esp), %ecx
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shrl $2, %ecx
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rep movsl
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/* Activate the right segment descriptor real mode. */
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ljmp $0x28, $RELOCATED(1f)
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1:
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.code16
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/* 16 bit code from here on... */
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/* Load the segment registers w/ properly configured
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* segment descriptors. They will retain these
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* configurations (limits, writability, etc.) once
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* protected mode is turned off.
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*/
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mov $0x30, %ax
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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mov %ax, %ss
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/* Turn off protection */
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movl %cr0, %eax
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andl $~PE, %eax
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movl %eax, %cr0
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/* Now really going into real mode */
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ljmp $0, $RELOCATED(1f)
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1:
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movw $0x0, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* This is a FAR JMP to the OS waking vector. The C code changed
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* the address to be correct.
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*/
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.byte 0xea
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__wakeup_offset = RELOCATED(.)
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.word 0x0000
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__wakeup_segment = RELOCATED(.)
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.word 0x0000
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.globl __wakeup_size
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__wakeup_size:
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.long . - __wakeup
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