1d6eeff171
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI ECAM Resource Consumption settings. The changes include specifying a QWordMemory resource template, accommodating non-cacheable, read-write attributes, and adjusting the address range. Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
83 lines
2.6 KiB
Text
83 lines
2.6 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_extern.asl>
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#if CONFIG(CHROMEOS_NVS)
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/* ChromeOS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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/* Operating system enumeration. */
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Name (OSYS, 0)
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/* 0 => PIC mode, 1 => APIC Mode */
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Name (PICM, 0)
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/* Power state (AC = 1) */
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Name (PWRS, 1)
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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PICM = Arg0
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}
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#if CONFIG(ECAM_MMCONF_SUPPORT)
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Scope(\_SB) {
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/* Base address of PCIe config space */
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Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
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/* Length of PCIe config space, 1MB each bus */
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Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
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/* PCIe Configuration Space */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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/* From the Linux documentation (Documentation/PCI/acpi-info.rst):
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* [6] PCI Firmware 3.2, sec 4.1.2:
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* If the operating system does not natively comprehend reserving the
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* MMCFG region, the MMCFG region must be reserved by firmware. The
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* address range reported in the MCFG table or by _CBA method (see Section
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* 4.1.3) must be reserved by declaring a motherboard resource. For most
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* systems, the motherboard resource would appear at the root of the ACPI
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* namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
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* the resources in this case should not be claimed in the root PCI bus's
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* _CRS. The resources can optionally be returned in Int15 E820 or
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* EFIGetMemoryMap as reserved memory but must always be reported through
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* ACPI as a motherboard resource.
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*/
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Device (PERC) // PCI ECAM Resource Consumption
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{
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Name (_HID, EisaId("PNP0C02"))
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Method (_CRS, 0, Serialized)
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{
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Name (RBUF, ResourceTemplate ()
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{
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QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed,
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NonCacheable, ReadWrite,
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0x0000000000000000, // Granularity
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0x0000000000000000, // _MIN
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0x0000000000000001, // _MAX
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0x0000000000000000, // Translation
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0x0000000000000002, // _Len
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,, _Y00, AddressRangeMemory, TypeStatic)
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})
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CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MIN, MIN1)
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CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MAX, MAX1)
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CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._LEN, LEN1)
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MIN1 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
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MAX1 = (MIN1 + CONFIG_ECAM_MMCONF_LENGTH -1)
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LEN1 = CONFIG_ECAM_MMCONF_LENGTH
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Return (RBUF)
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}
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}
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}
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#endif
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