1bd0c0c497
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/acpi.h>
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#include <soc/pci_ids.h>
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#include <reg_script.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/lpc.h>
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#include "chip.h"
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static const struct reg_script lpc_serirq_enable[] = {
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/* Setup SERIRQ, enable continuous mode */
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REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
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#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
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REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
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#endif
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REG_SCRIPT_END
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};
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static void enable_lpc_decode(struct device *lpc)
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{
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const struct soc_intel_apollolake_config *config;
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if (!lpc || !lpc->chip_info)
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return;
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config = lpc->chip_info;
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/* Enable requested fixed IO decode ranges */
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pci_write_config16(lpc, LPC_EN, config->lpc_dec);
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/* Enable generic IO decode ranges */
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pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec);
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}
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static void lpc_init(struct device *dev)
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{
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enable_lpc_decode(dev);
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reg_script_run_on_dev(dev, lpc_serirq_enable);
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}
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static void soc_lpc_add_io_resources(device_t dev)
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{
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struct resource *res;
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/* Add the default claimed legacy IO range for the LPC device. */
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res = new_resource(dev, 0);
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void soc_lpc_read_resources(device_t dev)
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{
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/* Get the PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add IO resources to LPC. */
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soc_lpc_add_io_resources(dev);
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}
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static struct device_operations device_ops = {
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.read_resources = &soc_lpc_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.write_acpi_tables = southbridge_write_acpi_tables,
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.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
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.init = &lpc_init
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};
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static const struct pci_driver soc_lpc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_APOLLOLAKE_LPC,
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};
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