coreboot-kgpe-d16/src/southbridge
Duncan Laurie e1e87e0ed6 haswell: Configure PCH power sharing for ULT
This reads PCH power levels via PCODE mailbox and writes the
values into the PMSYNC registers as indicated in the BWG.

Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4143
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:04:12 +01:00
..
amd AMD Hudson: Move function s3_resume_init_data to southbridge 2013-11-12 16:40:48 +01:00
broadcom x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
dmp dmp/vortex86ex: Move DMP specific POST code defines into one file 2013-11-24 05:36:36 +01:00
intel haswell: Configure PCH power sharing for ULT 2013-11-24 16:04:12 +01:00
nvidia usbdebug: Fix boards without EARLY_CBMEM_INIT 2013-10-22 21:35:05 +02:00
rdc x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
ricoh GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
sis usbdebug: Fix boards without EARLY_CBMEM_INIT 2013-10-22 21:35:05 +02:00
ti GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
via southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3` 2013-11-05 21:33:38 +01:00
Kconfig Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00
Makefile.inc Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00