1c6d8a9cf4
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
124 lines
3 KiB
C
124 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "chip.h"
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <timer.h>
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/* Fill up PMC resource structure */
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int pmc_soc_get_resources(struct pmc_resource_config *cfg)
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{
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cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
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cfg->pwrmbase_addr = PMC_BAR0;
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cfg->pwrmbase_size = PMC_BAR0_SIZE;
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cfg->abase_offset = PCI_BASE_ADDRESS_4;
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cfg->abase_addr = ACPI_BASE_ADDRESS;
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cfg->abase_size = ACPI_BASE_SIZE;
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return 0;
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}
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static int choose_slp_s3_assertion_width(int width_usecs)
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{
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int i;
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static const struct {
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int max_width;
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int value;
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} slp_s3_settings[] = {
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{
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.max_width = 60,
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.value = SLP_S3_ASSERT_60_USEC,
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},
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{
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.max_width = 1 * USECS_PER_MSEC,
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.value = SLP_S3_ASSERT_1_MSEC,
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},
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{
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.max_width = 50 * USECS_PER_MSEC,
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.value = SLP_S3_ASSERT_50_MSEC,
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},
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{
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.max_width = 2 * USECS_PER_SEC,
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.value = SLP_S3_ASSERT_2_SEC,
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},
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};
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for (i = 0; i < ARRAY_SIZE(slp_s3_settings); i++) {
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if (width_usecs <= slp_s3_settings[i].max_width)
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break;
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}
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/* Provide conservative default if nothing set in devicetree
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* or requested assertion width too large. */
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if (width_usecs <= 0 || i == ARRAY_SIZE(slp_s3_settings))
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i = ARRAY_SIZE(slp_s3_settings) - 1;
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printk(BIOS_DEBUG, "SLP S3 assertion width: %d usecs\n",
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slp_s3_settings[i].max_width);
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return slp_s3_settings[i].value;
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}
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static void set_slp_s3_assertion_width(int width_usecs)
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{
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uint32_t reg;
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uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
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int setting = choose_slp_s3_assertion_width(width_usecs);
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reg = read32((void *)gen_pmcon3);
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reg &= ~SLP_S3_ASSERT_MASK;
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reg |= setting << SLP_S3_ASSERT_WIDTH_SHIFT;
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write32((void *)gen_pmcon3, reg);
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}
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void pmc_soc_set_afterg3_en(const bool on)
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{
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void *const gen_pmcon1 = (void *)(soc_read_pmc_base() + GEN_PMCON1);
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uint32_t reg32;
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reg32 = read32(gen_pmcon1);
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if (on)
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reg32 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg32 |= SLEEP_AFTER_POWER_FAIL;
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write32(gen_pmcon1, reg32);
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}
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void pmc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg = config_of(dev);
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/* Set up GPE configuration */
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pmc_gpe_init();
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pmc_set_acpi_mode();
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if (cfg != NULL)
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set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
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/* Log power state */
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pch_log_state();
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/* Now that things have been logged clear out the PMC state. */
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pmc_clear_prsts();
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pmc_set_power_failure_state(true);
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}
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