336 lines
8.9 KiB
Python
336 lines
8.9 KiB
Python
# 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf
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#
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# JEDEC Standard No. 21-C
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# Page 4.1.2.12.3 – 1
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# Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
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# DDR4 SPD Document Release 3
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# UDIMM Revision 1.1
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# RDIMM Revision 1.1
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# LRDIMM Revision 1.1
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# NVDIMM Revision 1.0
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{
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# Byte 0: Number of Bytes Used / Number of Bytes in SPD Device /
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# CRC Coverage
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"SPD_Bytes_Used" : 4,
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"SPD_Bytes_Total" : 3,
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"CRC_Coverage" : 1,
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# Byte 1: SPD Revision
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"SPD_Revision" : 8,
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# Byte 2: Key Byte / DRAM Device Type
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"DRAM_Device_Type" : 8,
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# Byte 3: Key Byte / Module Type
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"Base_Module_Type" : 4,
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"Hybrid_Media" : 3,
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"Is_Hybrid" : 1,
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# Byte 4: SDRAM Density and Banks
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"SDRAM_Capacity" : 4,
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"Bank_Address_Bits" : 2,
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"Bank_Group_Bits" : 2,
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# Byte 5: SDRAM Addressing
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"Column_Address_Bits" : 3,
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"Row_Address_Bits" : 3,
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"Byte_5_reserved" : 2,
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# Byte 6: SDRAM Package Type
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"Signal_Loading" : 2,
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"Byte_6_reserved" : 2,
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"Die_Count" : 3,
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"SDRAM_Package_Type" : 1,
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# Byte 7: SDRAM Optional Features
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"Maximum_Activate_Count" : 4,
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"Maximum_Activate_Window" : 2,
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"Byte_7_reserved" : 2,
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# Byte 8: SDRAM Thermal and Refresh Options
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"Byte_8_reserved" : 8,
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# Byte 9: Other SDRAM Optional Features
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"Byte_9_reserved" : 5,
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"Soft_PPR" : 1,
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"Post_Package_Repair" : 2,
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# Byte 10: Secondary SDRAM Package Type
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"Secondary_Signal_Loading" : 2,
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"Secondary_DRAM_Densityt_Ratio" : 2,
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"Secondary_Die_Count" : 3,
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"Secondary_SDRAM_Package_Type" : 1,
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# Byte 11: Module Nominal Voltage, VDD
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"DRAM_VDD_1_2_V" : 2,
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"Byte_11_reserved" : 6,
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# Byte 12: Module Organization
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"SDRAM_Device_Width" : 3,
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"Number_of_Package_Ranks_per_DIMM" : 3,
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"Rank_Mix" : 1,
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"Byte_12_reserved" : 1,
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# Byte 13: Module Memory Bus Width
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"Primary_bus_width_in_bits" : 3,
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"Bus_width_extension_in_bits" : 2,
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"Byte_13_reserved" : 3,
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# Byte 14: Module Thermal Sensor
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"Byte_14_reserved" : 7,
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"Thermal_Sensor" : 1,
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# Byte 15: Extended Module Type
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"Extended_Base_Module_Type" : 4,
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"Byte_15_reserved" : 4,
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# Byte 16: Reserved
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"Byte_16_reserved" : 8,
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# Byte 17: Timebases
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"Fine_Timebase" : 2,
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"Medium_Timebase" : 2,
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"Byte_17_reserved" : 4,
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# Byte 18: SDRAM Minimum Cycle Time (tCKAVGmin)
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"tCKAVGmin" : 8,
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# Byte 19: SDRAM Maximum Cycle Time (tCKAVGmax)
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"tCKAVGmax" : 8,
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# Bytes 20 - 23: CAS Latencies Supported
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"CL_7_Supported" : 1,
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"CL_8_Supported" : 1,
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"CL_9_Supported" : 1,
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"CL_10_Supported" : 1,
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"CL_11_Supported" : 1,
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"CL_12_Supported" : 1,
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"CL_13_Supported" : 1,
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"CL_14_Supported" : 1,
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"CL_15_Supported" : 1,
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"CL_16_Supported" : 1,
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"CL_17_Supported" : 1,
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"CL_18_Supported" : 1,
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"CL_19_Supported" : 1,
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"CL_20_Supported" : 1,
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"CL_21_Supported" : 1,
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"CL_22_Supported" : 1,
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"CL_23_Supported" : 1,
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"CL_24_Supported" : 1,
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"CL_25_Supported" : 1,
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"CL_26_Supported" : 1,
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"CL_27_Supported" : 1,
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"CL_28_Supported" : 1,
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"CL_29_Supported" : 1,
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"CL_30_Supported" : 1,
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"CL_31_Supported" : 1,
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"CL_32_Supported" : 1,
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"CL_33_Supported" : 1,
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"CL_34_Supported" : 1,
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"CL_35_Supported" : 1,
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"CL_36_Supported" : 1,
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"Byte_23_reserved" : 1,
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"CL_range" : 1,
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# Byte 24: Minimum CAS Latency Time (tAAmin)
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"tAAmin" : 8,
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# Byte 25: Minimum RAS to CAS Delay Time (tRCDmin)
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"tRCDmin" : 8,
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# Byte 26: Minimum Row Precharge Delay Time (tRPmin)
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"tRPmin" : 8,
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# Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin)
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# / Minimum Active to Active/Refresh Delay Time
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# (tRCmin)
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"tRASmin_MSN" : 4,
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"tRCmin_MSN" : 4,
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"tRASmin_LSB" : 8,
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"tRCmin_LSB" : 8,
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# Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min)
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"tRFC1min_LSB" : 8,
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"tRFC1min_MSB" : 8,
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# Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min)
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"tRFC2min_LSB" : 8,
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"tRFC2min_MSB" : 8,
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# Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min)
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"tRFC4min_LSB" : 8,
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"tRFC4min_MSB" : 8,
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# Byte 36 - 37: Minimum Four Activate Window Delay Time
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# (tFAWmin)
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"tFAWmin_MSN" : 4,
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"Byte_36_reserved" : 4,
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"tFAWmin_LSB" : 8,
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# Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin),
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# different bank group
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"tRRD_Smin" : 8,
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# Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin),
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# same bank group
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"tRRD_Lmin" : 8,
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# Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank
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# group
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"tCCD_Lmin" : 8,
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# Byte 41 - 42: Minimum Write Recovery Time (tWRmin)
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"tWRmin_MSN" : 4,
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"Byte_41_reserved" : 4,
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"tWRmin_MSB" : 8,
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# Byte 43-45: Minimum Write to Read Time (tWTR_Smin),
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# different bank group / Minimum Write to Read Time
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# (tWTR_Lmin), same bank group
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"tWTR_Smin_MSN" : 4,
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"tWTR_Lmin_MSN" : 4,
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"tWTR_Smin_LSB" : 8,
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"tWTR_Lmin_LSB" : 8,
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# Byte 46~59: Reserved, Base Configuration Section
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"Byte_46_59_reserved" [14] : 8,
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# Byte 60: Connector to SDRAM Bit Mapping (DQ0-3)
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"DQ0_3" : 8,
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# Byte 61: Connector to SDRAM Bit Mapping (DQ4-7)
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"DQ4_7" : 8,
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# Byte 62: Connector to SDRAM Bit Mapping (DQ8-11)
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"DQ8_11" : 8,
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# Byte 63: Connector to SDRAM Bit Mapping (DQ12-15)
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"DQ12_15" : 8,
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# Byte 64: Connector to SDRAM Bit Mapping (DQ16-19)
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"DQ16_19" : 8,
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# Byte 65: Connector to SDRAM Bit Mapping (DQ20-23)
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"DQ20_23" : 8,
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# Byte 66: Connector to SDRAM Bit Mapping (DQ24-27)
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"DQ24_27" : 8,
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# Byte 67: Connector to SDRAM Bit Mapping (DQ28-31)
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"DQ28_31" : 8,
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# Byte 68: Connector to SDRAM Bit Mapping (CB0-3)
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"CB0_3" : 8,
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# Byte 69: Connector to SDRAM Bit Mapping (CB4-7)
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"CB4_7" : 8,
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# Byte 70: Connector to SDRAM Bit Mapping (DQ32-35)
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"DQ32_35" : 8,
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# Byte 71: Connector to SDRAM Bit Mapping (DQ36-39)
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"DQ36_39" : 8,
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# Byte 72: Connector to SDRAM Bit Mapping (DQ40-43)
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"DQ40_43" : 8,
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# Byte 73: Connector to SDRAM Bit Mapping (DQ44-47)
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"DQ44_47" : 8,
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# Byte 74: Connector to SDRAM Bit Mapping (DQ48-51)
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"DQ48_51" : 8,
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# Byte 75: Connector to SDRAM Bit Mapping (DQ52-55)
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"DQ52_55" : 8,
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# Byte 76: Connector to SDRAM Bit Mapping (DQ56-59)
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"DQ56_59" : 8,
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# Byte 77: Connector to SDRAM Bit Mapping (DQ60-63)
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"DQ60_63" : 8,
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# Bytes 78~116: Reserved, Base Configuration Section
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# Must be coded as 0x00
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"Byte_78_116_reserved" [39] : 8,
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# Byte 117: Fine Offset for Minimum CAS to CAS Delay Time
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# (tCCD_Lmin), same bank group
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"tCCD_Lmin_Fine_Offset" : 8,
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# Byte 118: Fine Offset for Minimum Activate to Activate Delay
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# Time (tRRD_Lmin), same bank group
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"tRRD_Lmin_Fine_Offset" : 8,
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# Byte 119: Fine Offset for Minimum Activate to Activate Delay
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# Time (tRRD_Smin), different bank group
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"tRRD_Smin_Fine_Offset" : 8,
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# Byte 120: Fine Offset for Minimum Active to Active/Refresh
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# Delay Time (tRCmin)
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"tRCmin_Fine_Offset" : 8,
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# Byte 121: Fine Offset for Minimum Row Precharge Delay
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# Time (tRPmin)
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"tRPmin_Fine_Offset" : 8,
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# Byte 122: Fine Offset for Minimum RAS to CAS Delay
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# Time (tRCDmin)
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"tRCDmin_Fine_Offset" : 8,
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# Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin)
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"tAAmin_Fine_Offset" : 8,
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# Byte 124: Fine Offset for SDRAM Maximum Cycle Time
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# (tCKAVGmax)
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"tCKAVGmax_Fine_Offset" : 8,
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# Byte 125: Fine Offset for SDRAM Minimum Cycle Time
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# (tCKAVGmin)
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"tCKAVGmin_Fine_Offset" : 8,
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# Byte 126 - 127: Cyclical Redundancy Code (CRC) for
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# Base Configuration Section
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"CRC_Base_Configuration" : 16,
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# Standard Module Parameters - Overlay Bytes 128~191
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# Module Specific Bytes for Unbuffered Memory Module Types
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# Byte 128: Raw Card Extension, Module Nominal Height
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"Module_Nominal_Height_Max" : 5,
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"Raw_Card_Extension" : 3,
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# Byte 129: Module Maximum Thickness
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"Module_Maximum_Thickness_Front" : 4,
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"Module_Maximum_Thickness_Back" : 4,
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# Byte 130: Reference Raw Card Used
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"Reference_Raw_Card" : 5,
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"Reference_Raw_Card_Revision" : 2,
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"Reference_Raw_Card_Extension" : 1,
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# Byte 131: Address Mapping from Edge Connector to DRAM
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"Rank_1_Mapping" : 1,
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"Byte_131_reserved" : 7,
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# Byte 132 - 191: Reserved
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"Byte_132_191_reserved" [60] : 8,
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# Unused
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# Byte 192 - 253: Unused
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"Byte_192_255_unused" [62] : 8,
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# Byte 254 - 255: CRC for SPD Block 1
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"CRC_SPD_Block_1" : 16,
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# Reserved
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# Byte 256 - 319: Reserved
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"Byte_256_319_reserved" [64] : 8,
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# End User Programmable
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# Byte 384 - 511
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"End_User_Programmable" [128] : 8
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}
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