5d994634a2
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
95 lines
1.9 KiB
Text
95 lines
1.9 KiB
Text
config BOOTBLOCK_CPU_INIT
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string
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default "cpu/samsung/exynos5250/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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config EXYNOS_ACE_SHA
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bool
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default n
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config SATA_AHCI
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bool
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default n
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config BL1_SIZE_KB
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int
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default 8
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_7f00: stack pointer
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# this may be used to calculate offsets
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config IRAM_BOTTOM
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hex
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default 0x02020000
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config IRAM_TOP
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hex
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default 0x02077fff
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config BOOTBLOCK_BASE
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hex
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default 0x02023400
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config ROMSTAGE_SIZE
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hex
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default 0x10000
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config CBFS_ROM_OFFSET
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# Calculated by BL1 + max bootblock size.
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hex "offset of CBFS data in ROM"
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default 0x0A000
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# TODO Change this to some better address not overlapping bootblock when
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# cbfstool supports creating header in arbitrary location.
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x2040
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# TODO We may probably move this to board-specific implementation files instead
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# of KConfig values.
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x02060000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x000017000
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# FIXME: This is for copying SPI content into SRAM temporarily and
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# will be removed when we have the SPI streaming driver implemented.
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config SPI_IMAGE_HACK
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hex
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default 0x02060000
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config IRAM_STACK
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hex
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default 0x02077f00
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# FIXME: other magic numbers that should probably go away
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config XIP_ROM_SIZE
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hex
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default ROMSTAGE_SIZE
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x40000000
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config SYS_TEXT_BASE
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hex "Executable code section"
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default 0x43e00000
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config COREBOOT_TABLES_SIZE
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hex
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default 0x100000
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