Felix Held 1d0154cee0 soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters ... Since FSP pre-populates the UPD struct with the non-zero default values, coreboot shouldn't set them to zero in the case that they aren't configured in the board's devicetree. Since all parameters being zero is a valid case, this patch adds another devicetree option that applying the devicetree settings for the USB2 PHY tuning depends on being set. BUG=b:161923068 Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-25 17:44:52 +00:00
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amd	soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters	2020-07-25 17:44:52 +00:00
cavium	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
intel	soc/intel/baytrail/southcluster.c: Align with Braswell	2020-07-25 10:23:25 +00:00
mediatek	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
nvidia	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
qualcomm	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
rockchip	soc/rockchip/rk3399/display.c: Add missing include	2020-07-14 16:11:42 +00:00
samsung	soc/samsung/exynos5420: Drop dead code	2020-07-09 21:37:01 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00