00a220877c
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Therefore, unlike the previous Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. by combining with EDK II, and it has no entry points for easily building it into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. AGESA reports the memory map to coreboot via HOBs returned from fsp_memory_init(). * AGESA currently sets up MTRRs, as in most older generations. Take ownership back immediately before running ramstage. * Remove cbmem initialization, as the FSP driver handles this. * Add chipset_handle_reset() for compatibility. * Top of memory is determined by the FSP driver checking the HOBs passed from AGESA. Note that relying on the TOM register happens to be misleading when UMA is below 4GB. BUG=b:147042464 TEST=Boot trembyle to payload Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <bootstate.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <romstage_handoff.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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#include <fsp/api.h>
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/* Supplied by i2c.c */
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extern struct device_operations picasso_i2c_mmio_ops;
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extern const char *i2c_acpi_name(const struct device *dev);
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struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = picasso_init_cpus,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCIE0_DEVFN:
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return "PBR4";
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case PCIE1_DEVFN:
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return "PBR5";
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case PCIE2_DEVFN:
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return "PBR6";
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case PCIE3_DEVFN:
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return "PBR7";
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case PCIE4_DEVFN:
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return "PBR8";
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case HDA1_DEVFN:
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return "AZHD";
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case LPC_DEVFN:
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return "LPCB";
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case SMBUS_DEVFN:
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return "SBUS";
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case XHCI0_DEVFN:
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return "XHC0";
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case XHCI1_DEVFN:
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return "XHC1";
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default:
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return NULL;
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}
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};
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struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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else if (dev->path.type == DEVICE_PATH_PCI)
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sb_enable(dev);
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else if (dev->path.type == DEVICE_PATH_MMIO)
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if (i2c_acpi_name(dev) != NULL)
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dev->ops = &picasso_i2c_mmio_ops;
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}
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static void soc_init(void *chip_info)
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{
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fsp_silicon_init(acpi_is_wakeup_s3());
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southbridge_init(chip_info);
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setup_bsp_ramtop();
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}
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static void soc_final(void *chip_info)
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{
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southbridge_final(chip_info);
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}
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struct chip_operations soc_amd_picasso_ops = {
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CHIP_NAME("AMD Picasso SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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