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Bernardo Perez Priego 1d8568c914 ec/google/wilco: Set minimum UCSI_ACPI region length
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB
with 32 Bytes alignment, this region holds smaller entries without having to reserve a
whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with
4 KB alignment.

The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached.
Cache mapping is set on page boundaries and all IMD Small is within the same page.
If another driver maps the memory as write-back before the UCSI driver is loaded then
the UCSI driver will fail to map the memory as not cached.

Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will
now be located within its own page. This patch will force UCSI_ACPI region to be
located in IMD Large region.

BUG=b:144826008

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Id00e76dca240279773a95c8054831e05df390664
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18 11:19:49 +00:00
3rdparty Populate 3rdparty/amd_blobs/ 2020-01-05 23:54:24 +00:00
Documentation documentation: Add documentation on setting up mainboard GPIOs 2020-01-18 10:58:36 +00:00
LICENSES LICENSES: Add licenses used in the coreboot repo 2019-10-30 08:23:51 +00:00
configs configs: Build test flashconsole 2020-01-10 15:13:10 +00:00
payloads libpayload: cbgfx: Support drawing a box with rounded corners 2020-01-14 18:25:36 +00:00
src ec/google/wilco: Set minimum UCSI_ACPI region length 2020-01-18 11:19:49 +00:00
util autoport: Improve formatting of EC ASL code 2020-01-16 13:21:56 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Add pmh7tool binary 2019-11-27 09:05:55 +00:00
.gitmodules submodules: Add 3rdparty/amd_blobs 2019-10-31 12:28:38 +00:00
.gitreview
AUTHORS Updated AUTHORS file for src/drivers 2019-10-22 12:55:27 +00:00
COPYING
MAINTAINERS MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A 2020-01-02 14:35:41 +00:00
Makefile util/kconfig: Move coreboot specific changes into Makefile.inc 2019-11-27 23:27:29 +00:00
Makefile.inc Make: Add supermicro/smcbiosinfo to tools 2020-01-08 16:24:04 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc
toolchain.inc Makefile: Remove romcc 2019-12-27 08:59:59 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.