1b79b86def
This enables SLP_S0 for x11 boards. Change-Id: I7240ed631bf72b1d3c9ea887da43772781c80b45 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org>
235 lines
6.7 KiB
Text
235 lines
6.7 KiB
Text
chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# FSP Configuration
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "SaGv" = "SaGv_Disabled"
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# Enable SGX
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register "sgx_enable" = "1"
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register "PrmrrSize" = "128 * MiB"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# SATA configuration
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register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 1, \
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[5] = 1, \
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[6] = 1, \
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[7] = 1, \
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}"
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register "SataPortsDevSlp" = "{\
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[0] = 0, \
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[1] = 0, \
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[2] = 0, \
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[3] = 0, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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# superspeed_inter-chip_supplement (SSIC) disabled
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register "SsicPortEnable" = "0"
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# USB
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register "usb2_ports" = "{
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[0] = USB2_PORT_EMPTY,
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[1] = USB2_PORT_EMPTY,
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[2] = USB2_PORT_EMPTY,
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[3] = USB2_PORT_EMPTY,
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[4] = USB2_PORT_EMPTY,
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[5] = USB2_PORT_EMPTY,
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[6] = USB2_PORT_EMPTY,
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[7] = USB2_PORT_EMPTY,
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[8] = USB2_PORT_EMPTY,
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[9] = USB2_PORT_EMPTY,
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[10] = USB2_PORT_EMPTY,
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[11] = USB2_PORT_EMPTY,
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[12] = USB2_PORT_EMPTY,
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[13] = USB2_PORT_EMPTY,
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}"
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register "usb3_ports" = "{
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[0] = USB3_PORT_EMPTY,
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[1] = USB3_PORT_EMPTY,
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[2] = USB3_PORT_EMPTY,
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[3] = USB3_PORT_EMPTY,
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[4] = USB3_PORT_EMPTY,
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[5] = USB3_PORT_EMPTY,
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[6] = USB3_PORT_EMPTY,
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[7] = USB3_PORT_EMPTY,
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[8] = USB3_PORT_EMPTY,
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[9] = USB3_PORT_EMPTY,
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}"
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# LPC
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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register "s0ix_enable" = "1"
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register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
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register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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# VR Settings Configuration for 4 Domains
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# ICC_MAX = 0 (Auto)
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# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
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# Disable PS4 powerstate in S0ix, thus no package C10 support
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# psi threshold is using FSP default values
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0 ,\
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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# No extra VR mailbox command
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register "SendVrMbxCmd" = "0"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 off end # CPU PCIe Port 10 (x16)
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device pci 01.1 off end # CPU PCIe Port 11 (x8)
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device pci 01.2 off end # CPU PCIe Port 12 (x4)
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device pci 02.0 off end # Integrated Graphics Device (IGD)
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device pci 04.0 on end # SA thermal subsystem
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device pci 05.0 off end # Imaging Unit
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device pci 08.0 off end # Gaussion Mixture Model (GMM)
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 off end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1b.0 off end # PCH PCIe Port 17
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device pci 1b.1 off end # PCH PCIe Port 18
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device pci 1b.2 off end # PCH PCIe Port 19
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device pci 1b.3 off end # PCH PCIe Port 20
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device pci 1c.0 off end # PCH PCIe Port 1
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device pci 1c.1 off end # PCH PCIe Port 2
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device pci 1c.2 off end # PCH PCIe Port 3
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device pci 1c.3 off end # PCH PCIe Port 4
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device pci 1c.4 off end # PCH PCIe Port 5
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device pci 1c.5 off end # PCH PCIe Port 6
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device pci 1c.6 off end # PCH PCIe Port 7
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device pci 1c.7 off end # PCH PCIe Port 8
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device pci 1d.0 off end # PCH PCIe Port 9
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device pci 1d.1 off end # PCH PCIe Port 10
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device pci 1d.2 off end # PCH PCIe Port 11
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device pci 1d.3 off end # PCH PCIe Port 12
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device pci 1d.4 off end # PCH PCIe Port 13
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device pci 1d.5 off end # PCH PCIe Port 14
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device pci 1d.6 off end # PCH PCIe Port 15
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device pci 1d.7 off end # PCH PCIe Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # SPI #0
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device pci 1f.0 on # LPC Interface
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chip superio/common
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device pnp 2e.0 on end
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end
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI Controller
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device pci 1f.6 off end # GbE
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device pci 1f.7 off end # Intel Trace Hub
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end
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end
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