Felix Held 1ed5a63c8c soc/amd/cezanne: add GNB IOAPIC support ... To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-09 18:11:21 +00:00
..
cezanne	soc/amd/cezanne: add GNB IOAPIC support	2021-05-09 18:11:21 +00:00
common	soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table	2021-05-09 18:09:36 +00:00
picasso	soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT	2021-05-09 18:09:20 +00:00
stoneyridge	soc/amd: factor out ACPI ALIB function numbers to common code	2021-05-08 17:56:10 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00