fdb3a8d07d
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
46 lines
1.3 KiB
Text
46 lines
1.3 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/nvidia/tegra210
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device cpu_cluster 0 on
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end
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "2560"
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register "yres" = "1800"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "32"
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register "color_depth" = "12"
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# framebuffer resolution
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register "display_xres" = "1280"
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register "display_yres" = "800"
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register "href_to_sync" = "1"
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register "hfront_porch" = "80"
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register "hsync_width" = "80"
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register "hback_porch" = "80"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "4"
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register "vsync_width" = "4"
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register "vback_porch" = "4"
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register "refresh" = "60"
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# use value from kernel driver
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register "pixel_clock" = "304416000"
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register "win_opt" = "DSI_ENABLE"
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end
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