9cd99a1524
pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelpch/lockdown.h>
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#include <soc/pm.h>
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static void lpc_lockdown_config(int chipset_lockdown)
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{
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/* Set Bios Interface Lock, Bios Lock */
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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lpc_set_bios_interface_lock_down();
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lpc_set_lock_enable();
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}
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}
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static void pmc_lockdown_config(void)
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{
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uint8_t *pmcbase;
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u32 pmsyncreg;
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/* PMSYNC */
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pmcbase = pmc_mmio_regs();
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pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
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pmsyncreg |= PMSYNC_LOCK;
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write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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/* LPC lock down configuration */
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lpc_lockdown_config(chipset_lockdown);
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/* PMC lock down configuration */
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pmc_lockdown_config();
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}
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