coreboot-kgpe-d16/src/soc/intel
Divya Sasidharan 1ff0f54f03 soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 23:09:47 +01:00
..
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell soc/braswell: Add CPUID for D0 stepping 2016-01-14 23:09:47 +01:00
broadwell soc/intel/broadwell: Add back support for EHCI debug setup 2015-12-27 17:45:06 +01:00
common tree: drop last paragraph of GPL copyright header from new files 2016-01-13 20:35:40 +01:00
fsp_baytrail fsp_baytrail: Add additional PCI space above 4GB 2016-01-08 02:44:15 +01:00
skylake intel/skylake/pcr.c: error out on invalid size in pcr read/write 2016-01-14 19:15:58 +01:00