No description
Find a file
Sridhar Siricilla 205437b759 soc/intel/common: Fix cpu index calculation
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.

Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.

The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc  on each reboot.

TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.

The coreboot log with code instrumentation, before this patch:

[DEBUG]   my_apic_id:0x10 cpu_index: 0x6
[DEBUG]   my_apic_id:0x11 cpu_index: 0x6
[DEBUG]   my_apic_id:0x42 cpu_index: 0x6
[DEBUG]   my_apic_id:0x21 cpu_index: 0x6
[DEBUG]   my_apic_id:0x40 cpu_index: 0x6
[DEBUG]   my_apic_id:0x31 cpu_index: 0x6
[DEBUG]   my_apic_id:0x39 cpu_index: 0x6
[DEBUG]   my_apic_id:0xa cpu_index: 0x3
[DEBUG]   my_apic_id:0x0 cpu_index: 0x0
[DEBUG]   my_apic_id:0x8 cpu_index: 0x2
[DEBUG]   my_apic_id:0x4 cpu_index: 0x2
[DEBUG]   my_apic_id:0x28 cpu_index: 0x6
[DEBUG]   my_apic_id:0x2 cpu_index: 0x1
[DEBUG]   my_apic_id:0x38 cpu_index: 0x6
[DEBUG]   my_apic_id:0x29 cpu_index: 0x6
[DEBUG]   my_apic_id:0xe cpu_index: 0x5
[DEBUG]   my_apic_id:0x6 cpu_index: 0x2
[DEBUG]   my_apic_id:0x20 cpu_index: 0x6
[DEBUG]   my_apic_id:0x30 cpu_index: 0x6
[DEBUG]   my_apic_id:0x19 cpu_index: 0x6
[DEBUG]   my_apic_id:0xc cpu_index: 0x4
[DEBUG]   my_apic_id:0x18 cpu_index: 0x6

We can see same cpu_index for multiple cores before fix.

After this patch..
[DEBUG]   my_apic_id:0x10 cpu_index: 0x8
[DEBUG]   my_apic_id:019 cpu_index: 0xb
[DEBUG]   my_apic_id:0x11 cpu_index: 0x9
[DEBUG]   my_apic_id:0x18 cpu_index: 0xa
[DEBUG]   my_apic_id:0x40 cpu_index: 0x14
[DEBUG]   my_apic_id:0x30 cpu_index: 0x10
[DEBUG]   my_apic_id:0x42 cpu_index: 0x15
[DEBUG]   my_apic_id:0xc cpu_index: 0x6
[DEBUG]   my_apic_id:0x2 cpu_index: 0x1
[DEBUG]   my_apic_id:0x29 cpu_index: 0xf
[DEBUG]   my_apic_id:0xe cpu_index: 0x7
[DEBUG]   my_apic_id:0x20 cpu_index: 0xc
[DEBUG]   my_apic_id:0x0 cpu_index: 0x0
[DEBUG]   my_apic_id:0x31 cpu_index: 0x11
[DEBUG]   my_apic_id:0x28 cpu_index: 0xe
[DEBUG]   my_apic_id:0x21 cpu_index: 0xd
[DEBUG]   my_apic_id:0xa cpu_index: 0x5
[DEBUG]   my_apic_id:0x38 cpu_index: 0x12
[DEBUG]   my_apic_id:0x8 cpu_index:  0x4
[DEBUG]   my_apic_id:0x4 cpu_index: 0x2
[DEBUG]   my_apic_id:0x39 cpu_index: 0x13

Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09 04:44:00 +00:00
3rdparty Update vboot submodule to upstream main 2023-01-05 17:57:33 +00:00
configs configs: Add 64bit buildtest for prodrive/hermes 2022-12-16 17:22:13 +00:00
Documentation Docs/releases: Update board support doc for 4.17 & 4.18 branches 2023-01-09 02:41:07 +00:00
LICENSES src/mb: Update unlicensable files with the CC-PDDC SPDX ID 2022-08-13 19:25:12 +00:00
payloads payloads: Update GRUB2 stable version from 2.04 to 2.06 2023-01-04 07:15:48 +00:00
spd spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017 2022-12-24 23:35:31 +00:00
src soc/intel/common: Fix cpu index calculation 2023-01-09 04:44:00 +00:00
tests spd.h: Move enum ddr3_module_type to ddr3.h 2023-01-04 12:39:32 +00:00
util util/docker: Update setuptools to get dtc building 2022-12-25 13:22:13 +00:00
.checkpatch.conf checkpatch.conf: Ignore check for pointer comparisons to NULL 2022-09-22 15:13:35 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Add .vscode/ 2022-08-30 17:56:55 +00:00
.gitmodules Add SBOM (Software Bill of Materials) Generation 2022-08-22 14:48:46 +00:00
.gitreview
.mailmap .mailmap: Add a .mailmap file for git 2022-03-08 18:53:47 +00:00
AUTHORS arm/libgcc: Support signed 64-bit division 2022-08-13 17:20:32 +00:00
COPYING
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
MAINTAINERS MAINTAINERS: Add AMD mayan reference board 2022-12-05 14:26:46 +00:00
Makefile Add option to use Ada code in romstage 2022-12-17 20:48:06 +00:00
Makefile.inc Kconfig: Add option to compress ramstage with LZ4 2023-01-08 01:20:15 +00:00
README.md /: Update and rewrite README.md 2022-12-10 17:53:53 +00:00
toolchain.inc coreboot: Add support for include-what-you-use 2022-10-11 14:33:28 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).

With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.

Source code

All source code for coreboot is stored in git. It is downloaded with the command:

git clone https://review.coreboot.org/coreboot.git.

Code reviews are done in the project's Gerrit instance.

The code may be browsed via coreboot's Gitiles instance.

The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.

Supported Hardware

The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.

For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.

Releases

Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.

All releases are available on the coreboot download page.

Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.

Build Requirements and building coreboot

The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.

To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.

That same page goes through how to use QEMU to boot the build and see the output.

Website and Mailing List

Further details on the project, as well as links to documentation and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyrights and Licenses

Uncopyrightable files

There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.

"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."

https://guides.lib.umich.edu/copyrightbasics/copyrightability

Similar terms apply to other locations.

These uncopyrightable files include:

  • Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
  • Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, spd files as binary .spd or text *spd*.hex representing memory chip configuration.
  • Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.

As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.

If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.

Copyrights

The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.

Licenses

Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.

Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.

Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.

The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.

The Software Freedom Conservancy

Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.