a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
106 lines
3 KiB
C
106 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <soc/gpio.h>
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#include <soc/lpc.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <delay.h>
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static void pch_pcie_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
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/* Enable SERR */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_SERR;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Enable Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Set Cache Line Size to 0x10 */
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pci_write_config8(dev, 0x0c, 0x10);
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reg16 = pci_read_config16(dev, 0x3e);
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reg16 &= ~(1 << 0); /* disable parity error response */
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reg16 |= (1 << 2); /* ISA enable */
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pci_write_config16(dev, 0x3e, reg16);
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#ifdef EVEN_MORE_DEBUG
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reg32 = pci_read_config32(dev, 0x20);
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printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x24);
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printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x28);
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printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x2c);
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printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
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#endif
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, 0x06);
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pci_write_config16(dev, 0x06, reg16);
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reg16 = pci_read_config16(dev, 0x1e);
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pci_write_config16(dev, 0x1e, reg16);
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}
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static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
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{
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/* Set max snoop and non-snoop latency for the SOC */
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pci_mmio_write_config32(dev, off, 0x10031003);
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}
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static struct pci_operations pcie_ops = {
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pch_pcie_init,
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.enable = NULL,
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.scan_bus = pciexp_scan_bridge,
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.ops_pci = &pcie_ops,
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};
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static const unsigned short pcie_device_ids[] = {
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/* Sunrisepoint-LP */
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0x9d10, 0x9d11, 0x9d12, 0x9d13, 0x9d14, 0x9d15, 0x9d16, 0x9d17,
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0x9d18, 0x9d19, 0x9d1a, 0x9d1b,
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0
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};
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pcie_device_ids,
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};
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