coreboot-kgpe-d16/src/cpu
Arthur Heymans a5b06b9b57 cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB
This fixes building lenovo/x200 with VBOOT.
All supported CPUs have enough L2 cache to support this.

Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-10-05 12:50:43 +00:00
..
amd cpu/amd/pi/00730F01: Use common code for mp_init 2023-08-08 20:27:50 +00:00
armltd cpu: Add SPDX license headers to Makefiles 2023-08-06 19:26:55 +00:00
intel cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB 2023-10-05 12:50:43 +00:00
power9 src/cpu/power9: move part of scom.h to scom.c 2023-04-18 13:05:56 +00:00
qemu-power8
qemu-x86 x86: Add .data section support for pre-memory stages 2023-09-14 21:02:07 +00:00
x86 cpu/x86/mtrr/debug: rename variables in display_variable_mtrr 2023-09-20 18:18:59 +00:00
Kconfig cpu: Enable per-CPUID microcode loading in CBFS 2023-07-08 12:06:00 +00:00
Makefile.inc cpu: Add SPDX license headers to Makefiles 2023-08-06 19:26:55 +00:00