f18abab200
Following the same reasoning as commit
d3043313a9 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
71 lines
1.1 KiB
Text
71 lines
1.1 KiB
Text
if BOARD_HP_DL145_G3
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_F
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select DIMM_DDR2
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select DIMM_REGISTERED
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_BROADCOM_BCM21000
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select SOUTHBRIDGE_BROADCOM_BCM5785
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select SUPERIO_SERVERENGINES_PILOT
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select SUPERIO_NSC_PC87417
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select LIFT_BSP_APIC_ID
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select BOARD_ROMSIZE_KB_512
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select QRANK_DIMM_SUPPORT
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select K8_ALLOCATE_IO_RANGE
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default hp/dl145_g3
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config DCACHE_RAM_BASE
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hex
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default 0xcc000
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config DCACHE_RAM_SIZE
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hex
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default 0x04000
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config APIC_ID_OFFSET
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hex
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default 0x8
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "ProLiant DL145 G3"
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x6
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 15
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endif # BOARD_HP_DL145_G3
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