cf2ac543a0
This change adds support for allocating resources for PCI express hotplug bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of non-prefetchable memory, and 8 KiB of I/O space to any device with the PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which indicates hot-plugging capability. The resource allocation is configurable, please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig. In order to support the allocation of hotplugged PCI buses, a new field is added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-busses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
#ifndef DEVICE_PCIEXP_H
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#define DEVICE_PCIEXP_H
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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enum aspm_type {
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PCIE_ASPM_NONE = 0,
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PCIE_ASPM_L0S = 1,
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PCIE_ASPM_L1 = 2,
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PCIE_ASPM_BOTH = 3,
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};
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#define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16
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#define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET)
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#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
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#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
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/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
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void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn);
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void pciexp_scan_bridge(struct device *dev);
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extern struct device_operations default_pciexp_ops_bus;
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#if CONFIG(PCIEXP_HOTPLUG)
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void pciexp_hotplug_scan_bridge(struct device *dev);
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extern struct device_operations default_pciexp_hotplug_ops_bus;
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#endif /* CONFIG(PCIEXP_HOTPLUG) */
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unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap);
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#endif /* DEVICE_PCIEXP_H */
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