No description
21a097aedc
This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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3rdparty | ||
Documentation | ||
payloads | ||
src | ||
util | ||
.clang-format | ||
.gitignore | ||
.gitmodules | ||
.gitreview | ||
COPYING | ||
MAINTAINERS | ||
Makefile | ||
Makefile.inc | ||
README | ||
toolchain.inc |
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * make * gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) Optional: * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig' and 'make nconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.