Felix Held 224b578420 soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings ... I'm not 100% sure if this should rather be duplicated from Picasso or commonized. Checked with the docs and this won't be compatible with Stoneyridge and one future product's PPR lacked the corresponding register. Some other chip has a compatible register layout, but a different number of PCIe GPP clock outputs, so the common code would need to use some SoC-dependent defines and possibly a SoC-specific lookup table for the mapping which is also not that great. TEST=Checked Cezanne PPR Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b6d0cb8d7eb0288d8a18fcb975dc377b2c6846a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54685 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-19 15:37:39 +00:00
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cezanne	soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings	2021-05-19 15:37:39 +00:00
common	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
picasso	soc/amd/picasso: move gpp_clk_req_setting definition to chip.h	2021-05-19 15:37:15 +00:00
stoneyridge	soc/amd: factor out ACPI ALIB function numbers to common code	2021-05-08 17:56:10 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00