6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
57 lines
905 B
Text
57 lines
905 B
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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// Intel PCI to PCI bridge 0:1e.0
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Device (PCIB)
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{
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Name (_ADR, 0x001e0000)
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Device (SLT1)
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{
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Name (_ADR, 0x00000000)
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Name (_PRW, Package(){ 11, 4 })
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}
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Device (SLT2)
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{
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Name (_ADR, 0x00010000)
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Name (_PRW, Package(){ 11, 4 })
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}
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Device (SLT3)
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{
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Name (_ADR, 0x00020000)
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Name (_PRW, Package(){ 11, 4 })
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}
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Device (SLT6)
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{
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Name (_ADR, 0x00050000)
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Name (_PRW, Package(){ 11, 4 })
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}
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Device (LANC)
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{
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Name (_ADR, 0x00080000)
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Name (_PRW, Package(){ 11, 3 })
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}
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Device (LANR)
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{
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Name (_ADR, 0x00000000)
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Name (_PRW, Package(){ 11, 3 })
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}
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// TODO: How many slots, where?
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// PCI Interrupt Routing.
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// If PICM is set, interrupts are routed over the i8259, otherwise
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// over the IOAPIC. (Really? If they're above 15 they need to be routed
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// fixed over the IOAPIC?)
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Method (_PRT)
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{
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#include "acpi/ich9_pci_irqs.asl"
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}
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}
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