b0f81518b5
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
55 lines
1.4 KiB
Text
55 lines
1.4 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define ENABLE_TPM
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
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// General Purpose Events
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//#include "acpi/gpe.asl"
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#include "acpi/thermal.asl"
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#include "../../../cpu/intel/haswell/acpi/cpu.asl"
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/haswell/acpi/haswell.asl>
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#include <southbridge/intel/lynxpoint/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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}
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
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}
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