coreboot-kgpe-d16/src/security/intel/txt
Arthur Heymans eeacd8349c cpu/intel/fit: Add the FIT table as a separate CBFS file
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in
this case the bootblock. After that a pointer to the BPM, Boot Policy
Manifest, containing the IBB digest needs to be added to the FIT
table.

If the fit table is inside the IBB, updating it with a pointer to the
BPM, would make the digest invalid.
The proper solution is to move the FIT table out of the bootblock.

The FIT table itself does not need to be covered by the digest as it
just contains pointers to structures that can by verified by the
hardware itself, such as microcode and ACMs (Authenticated Code
Modules).

Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:23:21 +00:00
..
common.c cbfs: Replace more instances of cbfs_boot_locate() with newer APIs 2021-03-17 08:10:20 +00:00
getsec.c sec/intel/txt: Add enable_getsec_or_reset function 2020-10-22 20:06:26 +00:00
getsec_enteraccs.S sec/intel/txt: Split MTRR setup ASM code into a macro 2020-10-22 20:06:54 +00:00
getsec_mtrr_setup.inc sec/intel/txt: Split MTRR setup ASM code into a macro 2020-10-22 20:06:54 +00:00
getsec_sclean.S sec/intel/txt: Add support for running SCLEAN in romstage 2020-11-04 23:31:11 +00:00
Kconfig sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable 2020-12-29 14:41:15 +00:00
logging.c src/{drivers,security}: Remove unused <string.h> 2021-02-16 17:19:01 +00:00
Makefile.inc cpu/intel/fit: Add the FIT table as a separate CBFS file 2021-03-19 11:23:21 +00:00
ramstage.c cbfs: Replace more instances of cbfs_boot_locate() with newer APIs 2021-03-17 08:10:20 +00:00
romstage.c haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
txt.h haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
txt_getsec.h sec/intel/txt: Add support for running SCLEAN in romstage 2020-11-04 23:31:11 +00:00
txt_platform.h intel/txt: Add txt_get_chipset_dpr function 2020-10-17 09:34:35 +00:00
txt_register.h haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00