6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include <soc/dsi.h>
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#include <soc/pll.h>
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void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
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{
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unsigned int txdiv0, txdiv1;
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u64 pcw;
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if (data_rate >= 2000 * MHz) {
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txdiv0 = 0;
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txdiv1 = 0;
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} else if (data_rate >= 1000 * MHz) {
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txdiv0 = 1;
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txdiv1 = 0;
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} else if (data_rate >= 500 * MHz) {
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txdiv0 = 2;
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txdiv1 = 0;
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} else if (data_rate > 250 * MHz) {
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/* (data_rate == 250MHz) is a special case that should go to the
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else-block below (txdiv0 = 4) */
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txdiv0 = 3;
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txdiv1 = 0;
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} else {
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/* MIN = 125 */
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assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
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txdiv0 = 4;
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txdiv1 = 0;
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}
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clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
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setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
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udelay(30);
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clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
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pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
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pcw <<= 24;
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pcw /= CLK26M_HZ;
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write32(&mipi_tx->pll_con0, pcw);
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clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
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udelay(30);
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setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
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/* BG_LPF_EN / BG_CORE_EN */
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write32(&mipi_tx->lane_con, 0x3fff0180);
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udelay(40);
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write32(&mipi_tx->lane_con, 0x3fff00c0);
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/* Switch OFF each Lane */
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clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
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setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
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}
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void mtk_dsi_reset(void)
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{
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write32(&dsi0->dsi_force_commit,
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DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
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write32(&dsi0->dsi_con_ctrl, 1);
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write32(&dsi0->dsi_con_ctrl, 0);
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}
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