Aaron Durbin 24079323d4 soc/amd/stoneyridge: provide alternate monotonic timer ... The TSC has been observed to be ticking at a non-constant rate in early boot. The root cause is still not known, but this misbehavior necessitates an alternative monotonic timer source. Use the perf TSC which ticks at 100 MHz. This also means the timestamp table is not accurate as well. Root cause of TSC rate instability needs to be resolved in order to fix that. BUG=b:72170796 Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>		2018-01-24 16:27:03 +00:00
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common	soc/amd/common: Make agesa_heap_base non-static	2018-01-19 19:47:43 +00:00
stoneyridge	soc/amd/stoneyridge: provide alternate monotonic timer	2018-01-24 16:27:03 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00