6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
86 lines
2.4 KiB
C
86 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boardid.h>
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#include <bootblock_common.h>
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#include <gpio.h>
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#include <device/mmio.h>
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#include <soc/gpio.h>
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#include <soc/i2c.h>
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#include <soc/mt6391.h>
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#include <soc/pericfg.h>
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#include <soc/spi.h>
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#include "gpio.h"
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static void i2c_set_gpio_pinmux(void)
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{
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gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1);
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gpio_set_mode(GPIO(SCL1), PAD_SCL1_FUNC_SCL1);
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gpio_set_mode(GPIO(SDA4), PAD_SDA4_FUNC_SDA4);
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gpio_set_mode(GPIO(SCL4), PAD_SCL4_FUNC_SCL4);
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}
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static void nor_set_gpio_pinmux(void)
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{
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/* Set driving strength of EINT4~EINT9 to 8mA
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* 0: 2mA
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* 1: 4mA
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* 2: 8mA
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* 3: 16mA
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*/
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/* EINT4: 0x10005B20[14:13] */
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clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
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/* EINT5~EINT9: 0x10005B30[2:1] */
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clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
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gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_pull(GPIO(EINT6), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_pull(GPIO(EINT7), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_pull(GPIO(EINT8), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_pull(GPIO(EINT9), GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SFWP_B);
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gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SFOUT);
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gpio_set_mode(GPIO(EINT6), PAD_EINT6_FUNC_SFCS0);
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gpio_set_mode(GPIO(EINT7), PAD_EINT7_FUNC_SFHOLD);
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gpio_set_mode(GPIO(EINT8), PAD_EINT8_FUNC_SFIN);
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gpio_set_mode(GPIO(EINT9), PAD_EINT9_FUNC_SFCK);
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}
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void bootblock_mainboard_early_init(void)
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{
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/* Clear UART0 power down signal */
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clrbits32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN);
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}
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void bootblock_mainboard_init(void)
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{
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/* adjust gpio params when external voltage is 1.8V */
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gpio_init(GPIO_EINT_1P8V);
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/* set i2c related gpio */
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i2c_set_gpio_pinmux();
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/* set nor related GPIO */
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nor_set_gpio_pinmux();
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/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
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board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
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gpio_output(GPIO(SRCLKENAI2), 1);
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/* Init i2c bus 2 Timing register for TPM */
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mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
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if (CONFIG(OAK_HAS_TPM2))
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gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
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0);
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setup_chromeos_gpios();
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 4)
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mt6391_enable_reset_when_ap_resets();
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}
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