24d1d4b472
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <usbdebug.h>
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#include <device/pci_def.h>
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#include "pch.h"
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/* Required for successful build, but currently empty. */
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void set_debug_port(unsigned int port)
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{
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/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
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}
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void enable_usbdebug(unsigned int port)
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{
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u32 dbgctl;
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device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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/* Force ownership of the Debug Port to the EHCI controller. */
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printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
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dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
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dbgctl |= (1 << 30);
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write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
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}
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