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Raul E Rangel 24ee0b5991 Revert "mb/google/zork: Increase RO section to 5MB" 
This reverts commit fddd101904188193197be10c8eae04e76386299b.

Reason for revert: With FSP compression and non serial FSP we now have enough space in RO.

Original change's description:
> mb/google/zork: Increase RO section to 5MB
>
> The current size is too small to fit all the depthcharge assets.
> Increasing it to 5MB gives us 648k of free space.
>
> $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT
> FMAP REGION: COREBOOT
> Name                           Offset     Type           Size   Comp
> cbfs master header             0x0        cbfs header        32 none
> fallback/romstage              0x80       stage          524316 none
> fallback/ramstage              0x80100    stage           96592 none
> config                         0x97ac0    raw               843 none
> revision                       0x97e80    raw               680 none
> spd.bin                        0x98180    spd              8192 none
> etc/sdcard0                    0x9a1c0    raw                 8 none
> locales                        0x9a200    raw               141 LZMA (166 decompressed)
> (empty)                        0x9a300    null             3224 none
> fspm.bin                       0x9afc0    fsp            720896 none
> (empty)                        0x14b000   null             3992 none
> fsps.bin                       0x14bfc0   fsp            327680 none
> pci1002,15d8,c1.rom            0x19c000   optionrom       54272 none
> pci1002,15d8,c4.rom            0x1a9480   optionrom       54272 none
> fallback/dsdt.aml              0x1b6900   raw             12727 none
> locale_hi.bin                  0x1b9b00   raw             10441 LZMA (239928 decompressed)
> ...
> locale_ko.bin                  0x254f80   raw             11282 LZMA (231168 decompressed)
> fallback/payload               0x257c00   simple elf      95169 none
> (empty)                        0x26f000   null           245656 none
> apu/amdfw                      0x2aafc0   raw           1277440 none
> (empty)                        0x3e2e00   null           688472 none
> bootblock                      0x48af80   bootblock          64 none
>
> BUG=b:130028876
> BRANCH=none
> TEST=Built image with depthcharge and booted.
>
> Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850
> Reviewed-by: Martin Roth <martinroth@google.com>

BUG=b:130028876, b:150746858
BRANCH=none
TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle
localhost ~ # flashrom -p host -r /tmp/main.bin
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
Calibrating delay loop... OK.
coreboot table found at 0xcbe54000.
Reading flash... SUCCESS

localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3
area:            22
area_offset:     0x00c00000
area_size:       0x00400000 (4194304)
area_name:       WP_RO

localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
SUCCESS

localhost ~ # flashrom -p host --wp-status
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
WP: status: 0x0094
WP: status.srp0: 1
WP: status.srp1: 0
WP: write protect is enabled.
WP: write protect range: start=0x00c00000, len=0x00400000

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 		2020-06-04 23:06:41 +00:00
3rdparty 3rdparty/amd_blobs: Update to include APCB_magic.bin 2020-05-27 15:59:45 +00:00
Documentation fw_config: Add firmware configuration interface 2020-06-02 16:40:04 +00:00
LICENSES drivers: Use SPDX identifiers 2020-05-25 22:19:21 +00:00
configs mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support 2020-05-16 17:38:46 +00:00
payloads payloads/libpayload/libc: Avoid NULL pointer dereference 2020-05-28 09:34:37 +00:00
src Revert "mb/google/zork: Increase RO section to 5MB" 2020-06-04 23:06:41 +00:00
tests tests: Always run all unit tests 2020-05-28 09:48:13 +00:00
util util/mb/google: add templates for puff boards 2020-06-04 15:52:45 +00:00
.checkpatch.conf
…
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
.gitmodules submodules: Add new submodule 3rdparty/cmocka 2020-05-26 16:20:49 +00:00
.gitreview
…
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
…
MAINTAINERS MAINTAINERS: Add entry for mb/ocp/tiogapass 2020-05-11 08:34:49 +00:00
Makefile Makefile: Use SPDX identifier 2020-05-23 21:03:17 +00:00
Makefile.inc Makefile: Add missing APCB_EDIT_TOOL variable 2020-05-27 16:00:05 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION 2020-05-26 15:04:08 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.