25962837ba
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/1205 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
117 lines
3.6 KiB
C
117 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <delay.h>
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#include <arch/coreboot_tables.h>
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#include "chip.h"
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <ec/lenovo/pmh7/pmh7.h>
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#include <ec/acpi/ec.h>
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#include <ec/lenovo/h8/h8.h>
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#include <northbridge/intel/i945/i945.h>
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#include <pc80/mc146818rtc.h>
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#include "dock.h"
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#include <arch/x86/include/arch/acpigen.h>
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static acpi_cstate_t cst_entries[] = {
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{ 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
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{ 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
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{ 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
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};
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int get_cst_entries(acpi_cstate_t **entries)
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{
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*entries = cst_entries;
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return ARRAY_SIZE(cst_entries);
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}
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static void mainboard_enable(device_t dev)
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{
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device_t dev0, idedev, sdhci_dev;
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u8 defaults_loaded = 0;
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ec_clr_bit(0x03, 2);
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if (inb(0x164c) & 0x08) {
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ec_set_bit(0x03, 2);
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ec_write(0x0c, 0x88);
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}
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/* If we're resuming from suspend, blink suspend LED */
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dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
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if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
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ec_write(0x0c, 0xc7);
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idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
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if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
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struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
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config->ide_enable_primary = 1;
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/* enable Ultrabay power */
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outb(inb(0x1628) | 0x01, 0x1628);
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ec_write(0x0c, 0x84);
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} else {
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/* disable Ultrabay power */
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outb(inb(0x1628) & ~0x01, 0x1628);
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ec_write(0x0c, 0x04);
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}
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/* Set SDHCI write protect polarity "SDWPPol" */
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sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0);
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if (sdhci_dev) {
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if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
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/* unlock */
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pci_write_config8(sdhci_dev, 0xf9, 0xfc);
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/* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */
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pci_write_config8(sdhci_dev, 0xfa, 0x20);
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/* restore lock */
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pci_write_config8(sdhci_dev, 0xf9, 0x00);
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}
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}
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if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
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printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
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defaults_loaded = 0;
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}
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if (!defaults_loaded) {
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printk(BIOS_INFO, "Restoring CMOS defaults\n");
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set_option("tft_brightness", &(u8[]){ 0xff });
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set_option("volume", &(u8[]){ 0x03 });
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/* set baudrate to 115200 baud */
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set_option("baud_rate", &(u8[]){ 0x00 });
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/* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
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set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
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set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
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}
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
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.enable_dev = mainboard_enable,
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};
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