3e3d969e6f
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <soc/gpio.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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/*
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* return family number and internal pad number in that community
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* by pad number and which community it is in.
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*/
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/* family number in high byte and inner pad number in lowest byte */
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void car_mainboard_pre_console_init(void)
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{
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uint32_t reg;
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uint32_t *pad_config_reg;
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/* Enable the UART hardware for COM1. */
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reg = 1;
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pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
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/*
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* Set up the pads to select the UART function
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* AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD
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* AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD
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*/
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pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD);
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write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
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M2));
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pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD);
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write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
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M2));
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}
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